ARM Cortex-A55

ARM Cortex-A55
General information
Launched2017
Designed byARM Holdings
Performance
Max. CPU clock rate1.25 GHz  to 2.31 GHz 
Cache
L1 cache32–128 KB (16–64 KB I-cache with parity, 16–64 KB D-cache) per core
L2 cache64–256 KB
L3 cache512 KB – 4 MB
Architecture and classification
ApplicationMobile
Instruction setARMv8.2-A
Physical specifications
Cores
  • 1–8 per cluster, multiple clusters
Products, models, variants
Product code name
  • Ananke
History
PredecessorARM Cortex-A53
SuccessorARM Cortex-A510

The ARM Cortex-A55 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A55 is a 2-wide decode in-order superscalar pipeline.

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