ARM Cortex-A510
| General information | |
|---|---|
| Launched | 2021 |
| Designed by | ARM Ltd. |
| Cache | |
| L1 cache | 64/128 KiB (32/64 KiB I-cache with parity, 32/64 KiB D-cache) per core |
| L2 cache | 0–512 KiB per complex |
| L3 cache | 128 KiB – 16 MiB (optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-A510 |
| Instruction set | ARMv9-A |
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessor | ARM Cortex-A55 |
| Successor | ARM Cortex-A520 |
The ARM Cortex-A510 is the successor to the ARM Cortex-A55 and the first ARMv9 high efficiency "LITTLE" CPU. It is the companion to the ARM Cortex-A710 "big" core. It is a clean-sheet 64-bit CPU designed by ARM Holdings' Cambridge design team.